Phase lock question

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Re: Phase lock question

Post by Ivan on Sun Jun 16, 2013 7:34 am

Oh, I see.

VBR from Ivan

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Re: Phase lock question

Post by Jalex2 on Sat Jun 15, 2013 2:35 pm

Hi  Ivan
Thanks for the confidence. The reason it was done in this way is because the 3.58mhz has to be locked to the incoming video color burst. What makes that even more complicated is the fact that the NTE797 has to be gated so it only looks at the burst and not all the other video. The gate signal for the NTE797 comes from the sync generator (CD22402, now obsolete) so if that 1Mhz clock signal is missing nothing works and the NTE797 won't lock. I built one of these a long time ago and it worked well so I know I can do it.  They will restore the video sync in any video that still has a fairly good color burst left.

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Re: Phase lock question

Post by Ivan on Sat Jun 15, 2013 7:15 am

Hi Jalex,
the loop filter may be the most difficult part of a PLL with 4046, if the pilot frequency varies (e.g. when synchronizing serial FSK communications). However, when the frequency is constant, the loop filter is not critical at all. This seems to be your case.
Your timebase solution sems a bit complicated to me. Isn't it possible to derive the clock directly from the crystal frequecy using a divider only? If this is not the case, I would probably use a much higher pilot frequency to minimize the jitter of the VCO in PLL. E.g. 3580/32=111,86KHz. If you use a divider by 9 in the PLL, you get 1006,7 KHz on its output.
PLL circuits have some "analog" features, so their implementation is a bit more troublesome than that of "purely digital" ones. Do not be afraid of them, though. You will tame 4046 in a short time !

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Re: Phase lock question

Post by Jalex2 on Fri Jun 14, 2013 3:07 pm

Thanks Ivan
I am sorry I didn't mention it was a different pin-out.  I just assumed you would know that as I had studied the data sheets on both of them.  After I thought about that a little more I understood it a little more. The only part left I am unsure about now is how to calculate the loop filter. The output of this chip is the clock signal for a video sync generator so it will need a very solid lock. The 7.9Khz is divided down from a 3.579545Mhz color burst crystal and another phase lock chip. (NTE797)  Most of the work I have done with phase lock chips has not been with dividers or multipliers so I don't have much experience there. My favorite one is just the old LM567 tone decoder an I have done a lot of interesting things with it but of course it's too simple to do anything like this. Another thing is when I have used phase lock chips they seem to be much more unforgiving about wiring mistakes than other cmos or TTL chips.

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Re: Phase lock question

Post by Ivan on Fri Jun 14, 2013 6:07 am

Hi Jalex,
you have found certainly, that the CD4046 is in no case a pin-to-pin replacement to NE564. The CD4046 consists of a VCO from cca 100 Hz to 1,3 MHZ (depends on Vcc), two phase comparators and some additional circuitry. I always had better results with the phase comparator II. (The comparator I is merely an EX-OR gate.)
You set the basic frequency and span of the VCO by a capacitor and two resistors. It is good to check the minimum and maximum frequency using a potentiometer as a variable voltage source on the VCO control input, with open loop. Set the VCO to swing e.g. from 990 kHz to 1010 kHz. The output of the VCO is your multiplied signal. Divide this signal by 128 and compare it with your pilot signal. BTW, 7,9*128 is greater than 1000 ! Make an appropriate loopback DC filter.

Good luck !
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Phase lock question

Post by Jalex2 on Thu Jun 13, 2013 2:31 pm

Hi
I would like to know if I can replace an NE564 with a CD4046. It is used in a multiplier circuit 7.9Khz to 1mhz.  (Muliplied by 128 using cd4040)  My book say the max frequency is 1.3mhz and that looks like it would be a little close.  I don't know too much about phase lock multipliers so would I run the cd4046 oscillator at 1 mhz or 7.9khz?

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